Vertical-cavity surface-emitting laser (VCSEL) offers some natural advantages over edge-emitting laser (EEL) like symmetrical laser beam and simple arrangement in two dimensional (2D) arrays, and are very attractive laser sources for a wide range of applications in optical interconnect, parallel links, free space communications, laser pumping, illumination,^[1–6] gesture recognition and 3D sensing.^[7,8] These applications all demand the device’s reliability, which largely depends on the thermal stability. For example, operating lifetime of the VCSEL decreases exponentially with temperature rising, and excessive temperature rise in the active region can reduce the VCSEL array’s reliability drastically.

Thus, it is important to investigate the thermal issue of the VCSEL and many researchers have made great efforts on it. Nakwaski et al.^[9] analyzed the current flow and temperature rise in etched-well VCSEL using the electrical analog method; Chen et al.^[10] developed an effective electrical conductivity model and considered size effects on the electrical, thermo-physical, and radiative properties; Choi et al.^[11] studied the thermal effects of 850-nm VCSEL using thermal-electric direct-coupled field analysis. These works provided valuable references both theoretically and experimentally, and usually focused on single VCSEL. Meanwhile it is common for many applications to take full advantage of the VCSEL array, so efforts have also been made for thermal characteristics of the VCSEL array. Wang et al.^[12] investigated the effects of oxide-aperture and substrate thickness. Holger Moench et al.^[13] simulated the heat flow in VCSEL array and presented an elongated rectangle shaped VCSEL array to achieve higher power. However, those studies basically focused on thermal characteristics of the single VCSEL device or the whole array device. Researches aiming at improving thermal stability of the VCSEL array by designing a mesa arrangement according to the heat coupling among mesas are lacking. The mesa arrangement is of great potential to have strong effects on the interplay of heat flux among different mesas in the VCSEL array, without alteration of the wafer structure and extra fabrication process. The interaction of heat flux among mesas will finally affect the temperature distribution and consequently the whole device performance.

In this paper we put forward a specially designed VCSEL array with non-regular mesa arrangement in order to enhance the thermal stability and reach higher power without overlarge mesa area. A 3D thermoelectric coupling analysis is performed to compare the temperature distribution inside the VCSEL array with different configuration of mesas. Based on the analytical results, we redesign the arrangement of mesas in order to lower down the heat coupling among mesas. Then, effects of the optimization(redesigning) were investigated experimentally. Light-current (LI) performances under different heat sink temperatures of the optimized array were compared to devices with normal 4×4 square arrays. Furthermore, we studied the spectra and central wavelength shift of arrays with different mesa arrangement, from which the thermal resistances were calculated. At last, far field patterns of different devices were measured.

The scheme of a single 980-nm bottom-emitting VCSEL device and the array are shown in Fig. 1. Our wafer was grown using metal-organic chemical vapor deposition (MOVCD). The epitaxial structure is as follows: the active region consists of three groups of In_0.2Ga_0.8As/GaAs_0.92P_0.08 quantum wells which are surrounded by Al_0.2Ga_0.8As spacer layers to make up a 1λ cavity. The active region and spacer layers are sandwiched by the n-doped distributed Bragg reflector (n-DBR) and p-doped DBR (p-DBR). The n- and p-type DBR consists of 22.5 pairs of Al_0.12Ga_0.88As/Al_0.9Ga_0.1As and 30 pairs of Al_0.12Ga_0.88As/Al0.9Ga0.1As λ/4-thick layers, respectively. The oxide aperture, which is used for carrier and photon confinement, is located between the p-doped spacer layer and the p-DBR.

Fig. 1.

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	Fig. 1. (color online) Schematic view of bottom emitting (a) single VCSEL and (b) VCSEL array.

Circular mesas are etched on the p-doped side of the wafer by chlorine using inductively coupled plasma (ICP) equipment. After a selective oxidation process, SiO₂ is deposited on the surface of the mesas using plasma enhanced chemical vapor deposition (PECVD). Then the SiO₂ on the top of the mesas is etched away by fluorine using ICP equipment and the p-contact is formed by DC sputtered Ti/Pt/Au. The GaAs substrate is then reduced down and polished. After sputtering of Ge/Au/Ni/Au, the output window is made by the lift-off process and the antireflection layer is grown on part of the wafer to avoid back reflections into the cavity. Finally the wafer is split apart, bonded to a C-Mount heat sink and packaged into TO-3. Further details of the device structure and output characteristics are published in Ref. [14].

To quantify the temperature distribution, heat source distributions in the VCSEL must be determined. In the DBR and the substrate layers, thermal resistance is the main heat source. In the active region, heat mainly comes from non-radiative recombination and resistive heating.^[15]

Under steady state conditions, the electrical potential in the VCSEL is determined by the Laplace equation:

To consider the interface and boundary scattering effects of phonons and electrons,^[16,17] anisotropic material properties are used in the active layer and DBR region. The electrical conductivity σ in Eq. (1) is defined as

We had considered the temperature-caused variation of thermal conductivity^[19]

Finally, the Joule heating , the Auger recombination and non-radiative recombination compose the total heat:

Table 1 lists the material properties and structural parameters used in the simulation.

Table 1.

Table 1.

Table 1. Material properties used in the simulation. . K−1 C/J⋅kg−1⋅K−1 ρ/kg⋅m3 p-contact 132.2 19.32 p-DBR 332 Active layer 332 n-DBR 375.5 Substrate 327 5.32 n-contact 132.2 19.32 The 3D thermal-electrical coupled field analysis model was built using COMSOL Multiphysics®. The boundary conditions for our bottom emitting devices were set as: p-side of the device having large heat exchange with the heat sink while the n-side having much smaller heat exchange with the air and remaining room temperature.

Table 1. Material properties used in the simulation. .

The primary purpose of our simulation is to investigate the temperature variation tendency of arrays with different mesa edge distances. Therefore, specifically, device structure in our simulation was simplified. The oxide layer is thin enough to be omitted and the oxidized part is regarded to be adiabatic, so the mesa’s diameter was the same as the oxide aperture’s being 100 μm. Thus we only constructed four main heat sources of a VCSEL: p-DBR, active layer, n-DBR and the substrate, which are sufficient enough to explore the thermal influence of different mesa arrangements.

As shown in Fig. 2, it was a 4×4 square VCSEL array we simulated and we had performed calculations for arrays with 4 different mesa-edge distances: 50 μm, 100 μm, 150 μm, and 200 μm.

Fig. 2.

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	Fig. 2. (color online) (a) Top view of a bottom emitting 4×4 VCSEL array. ms1: Edge mesa space; ms2: Middle mesa space; em1: Edge mesas; em2: 2nd row of mesas. d is the distance of two mesas’ edges. (b) Real mesa diameter is 150 μm while the simulation diameter is 100 μm.

4.1. Simulation for 4×4 VCSEL array

The surface temperature distribution and details on the active layer plane when adding 3-A current were obtained. Figure 3 demonstrates that the mesa distance has an obvious influence on the thermal characteristics of the device, in favor of our expectation.

Fig. 3.

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	Fig. 3. (color online) Surface temperature distribution of 4×4 VCSEL arrays with different mesa edge distances d: (a) d = 50 μm; (b) d = 100 μm; (c) d = 150 μm; (d) d = 200 μm. The maximum temperature for each design is 372.0294 K, 359.5966 K, 352.8352 K, and 348.9016 K respectively.

Figure 4 illustrates the details of the temperature distribution on the active layer. As the mesa distance increases, the maximum temperature decreases with the temperatures in each mesa converging to the same value.

Fig. 4.

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	Fig. 4. (color online) Temperature distribution in different position on the active layer plane for VCSEL arrays with different mesa edge distances d. (a) d = 50 μm, (b) d = 100 μm, (c) d = 150 μm, (d) d = 200 μm.

To have a closer insight, we investigated 20 mesa edge distances varying from 50 μm to 350 μm as shown in Fig. 5(a) The temperature curve gets smooth as mesa distance increases.

Fig. 5.

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	Fig. 5. (color online) (a) Maximum temperature for VCSEL arrays with different mesa edge distances ranging from 50 μm to 350 μm and (b) illustrative interaction among mesas.

Simulation results above indicate that the mesa distance together with the number of mesas surrounding have the main influence on thermal interaction among mesas. We give our explanation by sorting mesas into three types: the corner type, edge type and central type, marked sky-blue, yellow and red color respectively as depicted in Fig. 5(b). The corner type mesas at least interact with two mesas nearby while the edge type with at least three and the central type at least four. Hence, central mesas reached the highest temperatures, edge type mesas the medium and corner type mesas the lowest. And as mesa distance increases, heat exchange among mesas decays, resulting in lower and closer temperature of different mesas.

4.2. Optimization of mesa arrangement

According to the simulation, mesa distance has proven to have non-negligible influence on thermal characteristics of the device. Larger mesa distance can help avoid more heat coupling. However, the result in Fig. 5(a) indicates that large mesa distance is not necessary, and besides, too large separation of mesas will cause other drawbacks like lower output power density and coherence. Hence, it is worthwhile as well as being feasible to look for a reasonable mesa arrangement in which mesas’ positions are appropriately modified instead of increasing the mesa distance simply. The designed VCSEL array with appropriate mesa distance and not oversized mesas’ area as shown in Fig. 6(b).

Fig. 6.

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	Fig. 6. (color online) Illustration of mesa arrangement on the VCSEL array’s surface. (a) Normal mesa arrangement with mesa center (edge) distance equals 250 μm (100); (b) optimized mesa arrangement. The mesa radius is 75 μm. The mesa center distances: = 250 μm, = 300 μm, and = 150 μm.

The priority in our optimizing process is to reduce the heat coupling among meas as much as possible and then comes the whole mesa area. We chose the normal 4×4 mesa arrangement as the initial arrangement. Compared to the normal device, the distances of mesas in the central part got larger in the optimized array, because heat coupling among them is more serious than other mesas’.

Also, the position of some mesas were modified. Two mesas at the corners were moved to the centers of left and right sides respectively. Three remaining mesas on the top and bottom sides were moved to the center in their original rows. The existence of interaction between mesas is visualized in Fig. 7 by red and green lines (coupling lines). According to Fig. 4(d), in the array with mesa edge distance of 200 μm, the maximum temperature difference of the most adjacent mesas is 1.64 °C. For mesas with larger distance, the temperature difference and heat coupling is thought to be negligible. Therefore, if the mesa center (edge) distance of two mesas is larger than equaling 424.26 μm (274.26 μm), we disregard the heat coupling of them. Coupling lines of normal array and optimized array sum to 42 and 36 respectively. After this transformation, the mesa-distribution area changed from 562500 μm² to 600000 μm². To be noted, area for larger array with mesa edge distance being 150 μm, is 810000 μm².

Fig. 7.

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	Fig. 7. (color online) Coupling lines (red solid lines) which indicate the existence of heat coupling between mesas in (a) normal VCSEL array and (b) optimized VCSEL array. The green solid–dashed line in panel (b) represents the max mesa distance ( ) that can be counted as a coupling line. CN: coupling number.

4.3. Simulation for optimized array

Using exactly the same material parameters, boundary conditions and driving current of the 4×4 square mesa arrangement VCSEL array, we performed a simulation for the optimized one using COMSOL Multiphysics^® again. Through the surface temperature distribution and details on the active layer in Fig. 8 we can see that its heat generation is between the array with mesa edge distance being 100 μm(center distance being 250 μm) and the one with mesa edge distance being 150 μm (center distance being 300 μm). It should be noted here that the optimized array’s area is smaller than the area of array with mesa edge distance being 150 μm.

Fig. 8.

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	Fig. 8. (color online) Surface temperature (a) and details distribution on active layer (b) for optimized VCSEL array. The maximum temperature of the device is 356.1709 K. em1, em2, ms1, ms2 have the same meanings as Fig. 2 defined but are in the horizontal direction here and mm means the middle row of mesas.

According to the simulation, we fabricated three kinds of VCSEL arrays with different mesa arrangement. 4×4 square array with mesa edge distances being 100 μm, 150 μm and the optimized array were fabricated as a bottom emitting VCSEL array on the same wafer with the same mesa diameter of 150 μm. The optimized array has an irregular distribution of mesa, but it requires no additional fabrication process except changes of lithography mask.

5.1. LI characteristics for different VCSEL arrays at different heat sink temperatures

LI characteristics in different heat sink temperatures were tested under the CW condition. Due to the limit of maximum current (5 A), our device testing equipment could not make the devices reach the thermal roll-over point. It could be seen from both the LI curves for different temperatures and the statistical histogram of maximum power per mesas’ area (the maximum power divided by the mesas’ distribution area) in Fig. 9 that higher outer temperature leads to lower output power, which is caused by additional losses introduced by extra heat. The maximum powers for devices with d = 100 μm at temperatures from 25 °C to 70 °C are 1.84 W, 1.60 W, 1.42 W, 1.21 W, and 1.00 W respectively. The maximum powers for devices with d = 150 μm are 2.19 W, 1.83 W, 1.65 W, 1.42 W, and 1.20 W respectively. Counterparts for optimized devices are 2.16 W, 1.99 W, 1.83 W, 1.60 W, and 1.44 W respectively. Obviously the performance of optimized-mesa-arrangement device excelled at almost every heat sink temperature. As for devices with d = 100 μm and d = 150 μm, the larger distance shows an apparent advantage to the shorter distance. However, we should note that enlarging the mesa distance leads to a larger mesas’ area and therefore the size of the device has a greater limit. Our optimized device can avoid this problem, realizing the highest power and maintaining an appropriate mesas’ area of 600000 μm².

Fig. 9.

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	Fig. 9. (color online) (a) Power density characteristics of three kinds of VCSEL arrays at different heat sink temperatures, (b) statistical histogram of maximum power per mesas’ area for different devices.

The bottom emitting VCSEL device is sort of a flip chip as its p side is mounted on the heat sink. Hence the outer heat was transferred directly from p-DBR to the active layer, the case in which diffusing the heat among mesas away as much as possible becomes so important. Since each single mesa has the same epitaxial structure, factors relevant to the macro-structure like mesa arrangement is the key to lowering the thermal interaction among mesas. Figure 10 demonstrated that a device with an optimized mesa arrangement had the lowest maximum power decline ratio (power drop), the proportion of maximum power reduction at higher temperature to maximum power at the last lower temperature. As heat sink temperature increased, the power drop remained the least for the optimized VCSEL array, coinciding with the prediction of our simulation and analysis. The power stability and consequently the device reliability in optimized optimal design was upgraded.

Fig. 10.

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	Fig. 10. (color online) Maximum power decline ratio at different heat sink temperatures.

5.2. Spectra for different VCSEL arrays

To further investigate the thermal stability of different types of devices, spectra and wavelength shift were tested. Working on a copper heat sink without heating and water-cooling, the central wavelength shift for different devices varied as illustrated in Fig. 11. The wavelength shift obeys

The measured wavelength-temperature variation ( ) is 0.07 nm/°C^[20] so the temperature rises for each device are 51.7 °C, 49.1 °C, and 46.6 °C respectively.

Fig. 11.

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	Fig. 11. (color online) Central wavelength shift (WS) for different VCSEL array with heat sink at room temperature.

For this condition, we can also calculate the thermal resistance defined as

where can be calculated using wavelength-temperature variation and dissipated power can be calculated by . So is derived by the difference of at different driving currents. The thermal resistances of different devices are listed in Table 2. In favor of our expectation, the optimized array has the smallest thermal resistances.

Table 2.

Table 2.

Table 2. Thermal resistance(K/W) of different devices. . Current scale in calculation 1 A to 3 A 1 A to 3.5 A 1 A to 4 A d = 100 μm 8.0582 8.5147 8.7415 d = 150 μm 8.7719 8.9171 8.9734 Optimized array 6.8939 7.5127 7.8880

Table 2. Thermal resistance(K/W) of different devices. .

When adding water cooling, self-generated heat from the VCSEL array was constantly transferred to the heat sink, the central wavelength shift got shrunk as shown in Fig. 12 In this situation the optimized array wins again in thermal stability. The temperature rises for each device are 41.4 °C, 41.3 °C, and 38.7 °C respectively. For this condition it is needless to compare the thermal resistances.

Fig. 12.

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	Fig. 12. (color online) Central wavelength shift (WS) for different VCSEL arrays with heat sink with water cooling.

5.3. Far field patterns for different VCSEL arrays

Far field patterns of different devices at 3.5 A were measured as illustrated in Fig. 13. Though with a non-central symmetry, the optimized device shows a nearly circular pattern as the normal arrays do. Values of divergence angles are reasonable, bigger than ones of an array with d = 100 μm and slightly smaller than ones of an array with d = 1 50 μm. So far, we have not found any negative influence of the non-central symmetry on the device’s performances.

Fig. 13.

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	Fig. 13. (color online) Far field patterns and divergences for different VCSEL arrays.

A 3D thermal-electrical coupled finite-element method was developed to investigate the thermal characteristics of a 980nm high power bottom emitting VCSEL array. The simulations showed that a different mesa arrangement had an effect on the heat coupling between mesas. Optimization of the mesa arrangement was performed in order to improve the thermal behavior of the VCSEL array device. In the experimental investigation of VCSEL arrays with three kinds of mesa arrangements, the optimized VCSEL array has shown obvious advantages on LI characteristics and its thermal stability excels according to the spectra and thermal resistance under different driving currents. The optimized array has an average reduction of 1.2312 K/W in thermal resistance compared to normal VCSEL arrays at different current scales. Besides, it can reach higher output power while maintaining a not oversized mesas’ area and far field patterns suggest that non-central symmetry will not bring a negative effect to the device. The arrangement of VCSEL mesa has been proven to have a positive influence on device performances. It can be concluded that our optimizing process has efficiently reduced the thermal interplay between mesas and is instructive to array design. Finally, our optimizing method is after all a qualitative one and promisingly can be improved to a more perfect, quantitative one.